Clock sources

The GECKO5Education/GECKO5Modular provide two fixed clock sources and one variable clock input, namely:

  1. A 50 MHz clock oscillator.

  2. A 75.25 MHz clock oscillator.

  3. A pixel-clock input (see the camera interface section).

Using the clock sources

In this section you find a VHDL and Verilog top-level and the corresponding lpf-file that you can use to use one/multiple of the above described clock sources.

Important

Although VHDL is case-insensitive, the lpf-file is not. Meaning that the port-names in the top-level entity need to be copied exactly in the lpf-file.

An example for a VHDL top-level entity is shown below:

library ieee;
use ieee.std_logic_1164.all;

entity toplevel is
  port ( clock1  : in  std_logic;
         Clock2  : in  std_logic );
end toplevel;

An example for a Verilog top-level is shown below:

module toplevel (
  input wire clock1,
             Clock2);
  ...
endmodule

To connect clock1 to the 50 MHz clock source and Clock2 to the 74.25Mhz clock, following lines can be added to the lpf-file:

LOCATE COMP "clock1" SITE "F1";
IOBUF  PORT "clock1" PULLMODE=NONE IO_TYPE=LVCMOS33;
FREQUENCY PORT "clock1" 50 MHZ;

LOCATE COMP "Clock2" SITE "G2";
IOBUF  PORT "Clock2" PULLMODE=NONE IO_TYPE=LVCMOS33;
FREQUENCY PORT "Clock2" 74.25 MHZ;

Important

  1. Note the case-sensitivity of the lpf-file.

  2. The tools require exactly one lpf-file, hence all assignments you use need to be in a single lpf-file.

Derived clocks

The Lattice ECP5-family of FPGA’s provide PLL’s to generate derived clocks. The oss-cad-suite provides for this purpose the (experimental) tool ecppll. This tool can generate up to four derived clocks from one of the clock sources. The usage of this tool can be shown by executing ecppll -h.

Note

The ecppll tool generates a Verilog file. It should be possible to replace the parameters of the Verilog file into generics in VHDL, and the wire-connections into port-maps in VHDL. However, this has not been tested at the moment of the writing of this page.

An example mapping of a PLL in a Verilog top-module is shown below:

 module toplevel ( input wire clock74_25MHz,
                              nReset,
                   .... );

...

   wire s_resetPll = ~nReset;
   wire s_feedbackClock, s_pixelClkX2, s_pixelClock;
   wire s_systemClock, s_systemClockX2, s_pllLocked;
 
   EHXPLLL #(
         .PLLRST_ENA("ENABLED"),
         .INTFB_WAKE("DISABLED"),
         .STDBY_ENABLE("DISABLED"),
         .DPHASE_SOURCE("DISABLED"),
         .OUTDIVIDER_MUXA("DIVA"),
         .OUTDIVIDER_MUXB("DIVB"),
         .OUTDIVIDER_MUXC("DIVC"),
         .OUTDIVIDER_MUXD("DIVD"),
         .CLKI_DIV(1),
         .CLKOP_ENABLE("ENABLED"),
         .CLKOP_DIV(4),
         .CLKOP_CPHASE(1),
         .CLKOP_FPHASE(0),
         .CLKOS_ENABLE("ENABLED"),
         .CLKOS_DIV(8),
         .CLKOS_CPHASE(1),
         .CLKOS_FPHASE(0),
         .CLKOS2_ENABLE("ENABLED"),
         .CLKOS2_DIV(10),
         .CLKOS2_CPHASE(1),
         .CLKOS2_FPHASE(0),
         .CLKOS3_ENABLE("ENABLED"),
         .CLKOS3_DIV(5),
         .CLKOS3_CPHASE(1),
         .CLKOS3_FPHASE(0),
         .FEEDBK_PATH("INT_OP"),
         .CLKFB_DIV(2)
     ) pll_1 (
         .RST(s_resetPll),
         .STDBY(1'b0),
         .CLKI(clock74_25MHz),
         .CLKOP(s_pixelClkX2),
         .CLKOS(s_pixelClock),
         .CLKOS2(s_systemClock),
         .CLKOS3(s_systemClockX2),
         .CLKFB(s_feedbackClock),
         .CLKINTFB(s_feedbackClock),
         .PHASESEL0(1'b0),
         .PHASESEL1(1'b0),
         .PHASEDIR(1'b1),
         .PHASESTEP(1'b1),
         .PHASELOADREG(1'b1),
         .PLLWAKESYNC(1'b0),
         .ENCLKOP(1'b0),
         .LOCK(s_pllLocked));
 ...
 endmodule

Summary

Below a table with all required information for each clock source:

Clock source:

FPGA pin:

FREQUENCY:

IO_TYPE:

Pull-up/down:

50 MHz

F1

50 MHZ

LVCMOS33

NONE

74.25 MHz

G2

74.25 MHZ

LVCMOS33

NONE