HDMI interface

The GECKO5Education/Modular provide a HDMI-interface. This interface is based around the TFP410 PanelBus Digital Transmitter, supporting up to Full HD (1080p). The implemented HDMI interface provides a RGB555 (15-bit RGB) color space.

Using the HDMI interface

In this section you find a VHDL and Verilog top-level and the corresponding lpf-file that you can use for the HDMI-interface.

Important

Although VHDL is case-insensitive, the lpf-file is not. Meaning that the port-names in the top-level entity need to be copied exactly in the lpf-file.

An example for a VHDL top-level entity is shown below:

library ieee;
use ieee.std_logic_1164.all;

entity toplevel is
  port ( pixelClock      : out std_logic;
         horizontalSync  : out std_logic;
         verticalSync    : out std_logic;
         activePixel     : out std_logic;
         red             : out std_logic_vector( 4 DOWNTO 0);
         green           : out std_logic_vector( 4 DOWNTO 0);
         blue            : out std_logic_vector( 4 DOWNTO 0);
         ... );
end toplevel;

An example for a Verilog top-level is shown below:

module toplevel (
  output wire       pixelClock,
                    horizontalSync,
                    verticalSync,
                    activePixel,
  output wire [4:0] red,
                    green,
                    blue,
  ...);
  ...
endmodule

The required entries in the lpf-file are:

LOCATE COMP "pixelClock" SITE "N4";
LOCATE COMP "horizontalSync" SITE "K4";
LOCATE COMP "verticalSync" SITE "K5";
LOCATE COMP "activePixel" SITE "L4";
LOCATE COMP "red[0]" SITE "B19";
LOCATE COMP "red[1]" SITE "A19";
LOCATE COMP "red[2]" SITE "B18";
LOCATE COMP "red[3]" SITE "A18";
LOCATE COMP "red[4]" SITE "A17";
LOCATE COMP "green[0]" SITE "P5";
LOCATE COMP "green[1]" SITE "N5";
LOCATE COMP "green[2]" SITE "L5";
LOCATE COMP "green[3]" SITE "J5";
LOCATE COMP "green[4]" SITE "B20";
LOCATE COMP "blue[0]" SITE "L3";
LOCATE COMP "blue[1]" SITE "M4";
LOCATE COMP "blue[2]" SITE "M3";
LOCATE COMP "blue[3]" SITE "N3";
LOCATE COMP "blue[4]" SITE "P4";
IOBUF PORT "pixelClock" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
IOBUF PORT "horizontalSync" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
IOBUF PORT "verticalSync" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
IOBUF PORT "activePixel" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
IOBUF PORT "red[0]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
IOBUF PORT "red[1]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
IOBUF PORT "red[2]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
IOBUF PORT "red[3]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
IOBUF PORT "red[4]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
IOBUF PORT "green[0]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
IOBUF PORT "green[1]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
IOBUF PORT "green[2]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
IOBUF PORT "green[3]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
IOBUF PORT "green[4]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
IOBUF PORT "blue[0]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
IOBUF PORT "blue[1]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
IOBUF PORT "blue[2]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
IOBUF PORT "blue[3]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
IOBUF PORT "blue[4]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;

Important

  1. Note the case-sensitivity of the lpf-file.

  2. The tools require exactly one lpf-file, hence all assignments you use need to be in a single lpf-file.

Designing a HDMI controller

The TFP410 converts a VGA protocol into the HDMI-signals. Note that not all televisions support all video-resolutions. Most computer monitors, however, do.

A nice web-site describing the video parameters can be found here. In the courses *CS-473: System programming for Systems-on-chip and CS-476: Embedded System Design at EPFL we use the HDMI-controller in HD (720p).

In case you do not have a monitor available Sandberg provides a HDMI Capture Link that acts as a webcam, supports most resolutions, and is supported in Windows, Linux, and MAC-OS.

Summary

Below the table with all required information for the HDMI-interface:

Name:

FPGA pin:

IO_TYPE:

Drive:

Name:

FPGA pin:

IO_TYPE:

Drive:

pixel clock

N4

LVCMOS33

4 mA

horizontal sync

K4

LVCMOS33

4 mA

vertical sync

K5

LVCMOS33

4 mA

active pixel

L4

LVCMOS33

4 mA

red bit 0

B19

LVCMOS33

4 mA

red bit 1

A19

LVCMOS33

4 mA

red bit 2

B18

LVCMOS33

4 mA

red bit 3

A18

LVCMOS33

4 mA

red bit 4

A17

LVCMOS33

4 mA

green bit 0

P5

LVCMOS33

4 mA

green bit 1

N5

LVCMOS33

4 mA

green bit 2

L5

LVCMOS33

4 mA

green bit 3

J5

LVCMOS33

4 mA

green bit 4

B20

LVCMOS33

4 mA

blue bit 0

L3

LVCMOS33

4 mA

blue bit 1

M4

LVCMOS33

4 mA

blue bit 2

M3

LVCMOS33

4 mA

blue bit 3

N3

LVCMOS33

4 mA

blue bit 4

P4

LVCMOS33

4 mA