Uart-interface (RS232)

The GECKO5Education/Modular provide a simple 2-wire UART (RS232).

Using the uart-interface

In this section you find a VHDL and Verilog top-level and the corresponding lpf-file that you can use for the uart-interface.

Important

Although VHDL is case-insensitive, the lpf-file is not. Meaning that the port-names in the top-level entity need to be copied exactly in the lpf-file.

An example for a VHDL top-level entity is shown below:

library ieee;
use ieee.std_logic_1164.all;

entity toplevel is
  port ( txd : out std_logic;
         rxd : in  std_logic;
         ... );
end toplevel;

An example for a Verilog top-level is shown below:

module toplevel (
  output wire txd,
  input  wire rxd,
  ...);
  ...
endmodule

The required entries in the lpf-file are:

LOCATE COMP "rxd" SITE "T1";
LOCATE COMP "txd" SITE "R1";
IOBUF PORT "rxd" PULLMODE=NONE IO_TYPE=LVCMOS33;
IOBUF PORT "txd" PULLMODE=NONE IO_TYPE=LVCMOS33;

Important

Note the case-sensitivity of the lpf-file.
The tools require exactly one lpf-file, hence all assignments you use need to be in a single lpf-file.

Uart-settings

In the courses *CS-473: System programming for Systems-on-chip and CS-476: Embedded System Design at EPFL we use the uart with following parameters:

Baud rate: 115200
Data Bits: 8
Flow Control: None
Parity: None
Stop Bits: 1

Summary

Below the table with all required information for the uart-interface:

Name:	FPGA pin:	IO_TYPE:	Description:
TxD	R1	LVCMOS33	Serial data out
RxD	T1	LVCMOS33	Serial data in