Synchronous DRAM (SDRAM)
The GECKO5Education/Modular have a 4M x 16Bits x 4Banks (32 Mbyte) Mobile Synchronous DRAM. The data sheet can be found here. The SDRAM is operated at 1.8V to reduce the overall energy consumption.
Using the SDRAM
In this section you find a VHDL and Verilog top-level and the corresponding lpf-file that you can use for the SDRAM.
Important
Although VHDL is case-insensitive, the lpf-file is not. Meaning that the port-names in the top-level entity need to be copied exactly in the lpf-file.
An example for a VHDL top-level entity is shown below:
library ieee;
use ieee.std_logic_1164.all;
entity toplevel is
port ( sdramClk : out std_logic;
sdramCke : out std_logic;
sdramCsN : out std_logic;
sdramRasN : out std_logic;
sdramCasN : out std_logic;
sdramWeN : out std_logic;
sdramDqmN : out std_logic_vector( 1 downto 0);
sdramAddr : out std_logic_vector(12 downto 0);
sdramBa : out std_logic_vector( 1 downto 0);
sdramData : inout std_logic_vector(15 downto 0);
...);
end toplevel;
An example for a Verilog top-level is shown below:
module toplevel (
output wire sdramClk,
output wire sdramCke,
sdramCsN,
sdramRasN,
sdramCasN,
sdramWeN,
output wire [1:0] sdramDqmN,
output wire [12:0] sdramAddr,
output wire [1:0] sdramBa,
inout wire [15:0] sdramData,
...);
...
endmodule
The required entries in the lpf-file are:
LOCATE COMP "sdramClk" SITE "G19";
LOCATE COMP "sdramCke" SITE "F17";
LOCATE COMP "sdramCsN" SITE "R20";
LOCATE COMP "sdramRasN" SITE "R18";
LOCATE COMP "sdramCasN" SITE "R17";
LOCATE COMP "sdramWeN" SITE "N18";
LOCATE COMP "sdramDqmN[0]" SITE "T17";
LOCATE COMP "sdramDqmN[1]" SITE "G20";
LOCATE COMP "sdramAddr[0]" SITE "P17";
LOCATE COMP "sdramAddr[1]" SITE "P20";
LOCATE COMP "sdramAddr[2]" SITE "N20";
LOCATE COMP "sdramAddr[3]" SITE "P16";
LOCATE COMP "sdramAddr[4]" SITE "H17";
LOCATE COMP "sdramAddr[5]" SITE "J20";
LOCATE COMP "sdramAddr[6]" SITE "H18";
LOCATE COMP "sdramAddr[7]" SITE "H20";
LOCATE COMP "sdramAddr[8]" SITE "J19";
LOCATE COMP "sdramAddr[9]" SITE "G16";
LOCATE COMP "sdramAddr[10]" SITE "P19";
LOCATE COMP "sdramAddr[11]" SITE "G18";
LOCATE COMP "sdramAddr[12]" SITE "F16";
LOCATE COMP "sdramBa[0]" SITE "P18";
LOCATE COMP "sdramBa[1]" SITE "R16";
LOCATE COMP "sdramData[0]" SITE "U20";
LOCATE COMP "sdramData[1]" SITE "U19";
LOCATE COMP "sdramData[2]" SITE "U18";
LOCATE COMP "sdramData[3]" SITE "U17";
LOCATE COMP "sdramData[4]" SITE "U16";
LOCATE COMP "sdramData[5]" SITE "T19";
LOCATE COMP "sdramData[6]" SITE "T20";
LOCATE COMP "sdramData[7]" SITE "T18";
LOCATE COMP "sdramData[8]" SITE "F18";
LOCATE COMP "sdramData[9]" SITE "F19";
LOCATE COMP "sdramData[10]" SITE "F20";
LOCATE COMP "sdramData[11]" SITE "E16";
LOCATE COMP "sdramData[12]" SITE "E17";
LOCATE COMP "sdramData[13]" SITE "E18";
LOCATE COMP "sdramData[14]" SITE "E20";
LOCATE COMP "sdramData[15]" SITE "E19";
IOBUF PORT "sdramClk" PULLMODE=NONE IO_TYPE=LVCMOS18;
IOBUF PORT "sdramCke" PULLMODE=NONE IO_TYPE=LVCMOS18;
IOBUF PORT "sdramCsN" PULLMODE=UP IO_TYPE=LVCMOS18;
IOBUF PORT "sdramRasN" PULLMODE=NONE IO_TYPE=LVCMOS18;
IOBUF PORT "sdramCasN" PULLMODE=NONE IO_TYPE=LVCMOS18;
IOBUF PORT "sdramWeN" PULLMODE=NONE IO_TYPE=LVCMOS18;
IOBUF PORT "sdramDqmN[0]" PULLMODE=NONE IO_TYPE=LVCMOS18;
IOBUF PORT "sdramDqmN[1]" PULLMODE=NONE IO_TYPE=LVCMOS18;
IOBUF PORT "sdramAddr[0]" PULLMODE=NONE IO_TYPE=LVCMOS18;
IOBUF PORT "sdramAddr[1]" PULLMODE=NONE IO_TYPE=LVCMOS18;
IOBUF PORT "sdramAddr[2]" PULLMODE=NONE IO_TYPE=LVCMOS18;
IOBUF PORT "sdramAddr[3]" PULLMODE=NONE IO_TYPE=LVCMOS18;
IOBUF PORT "sdramAddr[4]" PULLMODE=NONE IO_TYPE=LVCMOS18;
IOBUF PORT "sdramAddr[5]" PULLMODE=NONE IO_TYPE=LVCMOS18;
IOBUF PORT "sdramAddr[6]" PULLMODE=NONE IO_TYPE=LVCMOS18;
IOBUF PORT "sdramAddr[7]" PULLMODE=NONE IO_TYPE=LVCMOS18;
IOBUF PORT "sdramAddr[8]" PULLMODE=NONE IO_TYPE=LVCMOS18;
IOBUF PORT "sdramAddr[9]" PULLMODE=NONE IO_TYPE=LVCMOS18;
IOBUF PORT "sdramAddr[10]" PULLMODE=NONE IO_TYPE=LVCMOS18;
IOBUF PORT "sdramAddr[11]" PULLMODE=NONE IO_TYPE=LVCMOS18;
IOBUF PORT "sdramAddr[12]" PULLMODE=NONE IO_TYPE=LVCMOS18;
IOBUF PORT "sdramBa[0]" PULLMODE=NONE IO_TYPE=LVCMOS18;
IOBUF PORT "sdramBa[1]" PULLMODE=NONE IO_TYPE=LVCMOS18;
IOBUF PORT "sdramData[0]" PULLMODE=NONE IO_TYPE=LVCMOS18;
IOBUF PORT "sdramData[1]" PULLMODE=NONE IO_TYPE=LVCMOS18;
IOBUF PORT "sdramData[2]" PULLMODE=NONE IO_TYPE=LVCMOS18;
IOBUF PORT "sdramData[3]" PULLMODE=NONE IO_TYPE=LVCMOS18;
IOBUF PORT "sdramData[4]" PULLMODE=NONE IO_TYPE=LVCMOS18;
IOBUF PORT "sdramData[5]" PULLMODE=NONE IO_TYPE=LVCMOS18;
IOBUF PORT "sdramData[6]" PULLMODE=NONE IO_TYPE=LVCMOS18;
IOBUF PORT "sdramData[7]" PULLMODE=NONE IO_TYPE=LVCMOS18;
IOBUF PORT "sdramData[8]" PULLMODE=NONE IO_TYPE=LVCMOS18;
IOBUF PORT "sdramData[9]" PULLMODE=NONE IO_TYPE=LVCMOS18;
IOBUF PORT "sdramData[10]" PULLMODE=NONE IO_TYPE=LVCMOS18;
IOBUF PORT "sdramData[11]" PULLMODE=NONE IO_TYPE=LVCMOS18;
IOBUF PORT "sdramData[12]" PULLMODE=NONE IO_TYPE=LVCMOS18;
IOBUF PORT "sdramData[13]" PULLMODE=NONE IO_TYPE=LVCMOS18;
IOBUF PORT "sdramData[14]" PULLMODE=NONE IO_TYPE=LVCMOS18;
IOBUF PORT "sdramData[15]" PULLMODE=NONE IO_TYPE=LVCMOS18;
Important
Note the case-sensitivity of the lpf-file.
The tools require exactly one lpf-file, hence all assignments you use need to be in a single lpf-file.
Summary
Below the table with all required information for the HDMI-interface:
Name: |
FPGA pin: |
IO_TYPE: |
Active low/high: |
Name: |
FPGA pin: |
IO_TYPE: |
Active low/high: |
|---|---|---|---|---|---|---|---|
clock |
G19 |
LVCMOS18 |
active high |
||||
clock enable |
F17 |
LVCMOS18 |
active high |
chip select |
R20 |
LVCMOS18 |
active low |
row address select |
R18 |
LVCMOS18 |
active low |
column address select |
R17 |
LVCMOS18 |
active low |
write enable |
N18 |
LVCMOS18 |
active low |
byte enable lo |
T17 |
LVCMOS18 |
active low |
byte enable high |
G20 |
LVCMOS18 |
active low |
address 0 |
P17 |
LVCMOS18 |
active high |
address 1 |
P20 |
LVCMOS18 |
active high |
address 2 |
N20 |
LVCMOS18 |
active high |
address 3 |
P16 |
LVCMOS18 |
active high |
address 4 |
H17 |
LVCMOS18 |
active high |
address 5 |
J20 |
LVCMOS18 |
active high |
address 6 |
H18 |
LVCMOS18 |
active high |
address 7 |
H20 |
LVCMOS18 |
active high |
address 8 |
J19 |
LVCMOS18 |
active high |
address 9 |
G16 |
LVCMOS18 |
active high |
address 10 |
P19 |
LVCMOS18 |
active high |
address 11 |
G18 |
LVCMOS18 |
active high |
address 12 |
F16 |
LVCMOS18 |
active high |
bank select 0 |
P18 |
LVCMOS18 |
active high |
bank select 1 |
R16 |
LVCMOS18 |
active high |
data bit 0 |
U20 |
LVCMOS18 |
active high |
data bit 1 |
U19 |
LVCMOS18 |
active high |
data bit 2 |
U18 |
LVCMOS18 |
active high |
data bit 3 |
U17 |
LVCMOS18 |
active high |
data bit 4 |
U16 |
LVCMOS18 |
active high |
data bit 5 |
T19 |
LVCMOS18 |
active high |
data bit 6 |
T20 |
LVCMOS18 |
active high |
data bit 7 |
T18 |
LVCMOS18 |
active high |
data bit 8 |
F18 |
LVCMOS18 |
active high |
data bit 9 |
F19 |
LVCMOS18 |
active high |
data bit 10 |
F20 |
LVCMOS18 |
active high |
data bit 11 |
E16 |
LVCMOS18 |
active high |
data bit 12 |
E17 |
LVCMOS18 |
active high |
data bit 13 |
E18 |
LVCMOS18 |
active high |
data bit 14 |
E20 |
LVCMOS18 |
active high |
data bit 15 |
E19 |
LVCMOS18 |
active high |